Hongwu Jiang, Rui Liu 0005, Shimeng Yu. 8T XNOR-SRAM based Parallel Compute-in-Memory for Deep Neural Network Accelerator. In 63rd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2020, Springfield, MA, USA, August 9-12, 2020. pages 257-260, IEEE, 2020. [doi]
@inproceedings{Jiang0Y20,
title = {8T XNOR-SRAM based Parallel Compute-in-Memory for Deep Neural Network Accelerator},
author = {Hongwu Jiang and Rui Liu 0005 and Shimeng Yu},
year = {2020},
doi = {10.1109/MWSCAS48704.2020.9184455},
url = {https://doi.org/10.1109/MWSCAS48704.2020.9184455},
researchr = {https://researchr.org/publication/Jiang0Y20},
cites = {0},
citedby = {0},
pages = {257-260},
booktitle = {63rd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2020, Springfield, MA, USA, August 9-12, 2020},
publisher = {IEEE},
isbn = {978-1-7281-8058-8},
}