Hopscotch: A Hardware-Software Co-Design for Efficient Cache Resizing on Multi-Core SoCs

Zhe Jiang 0004, Kecheng Yang 0001, Nathan Fisher, Nan Guan, Neil C. Audsley, Zheng Dong 0002. Hopscotch: A Hardware-Software Co-Design for Efficient Cache Resizing on Multi-Core SoCs. IEEE Trans. Parallel Distrib. Syst., 35(1):89-104, January 2024. [doi]

@article{JiangYFGAD24,
  title = {Hopscotch: A Hardware-Software Co-Design for Efficient Cache Resizing on Multi-Core SoCs},
  author = {Zhe Jiang 0004 and Kecheng Yang 0001 and Nathan Fisher and Nan Guan and Neil C. Audsley and Zheng Dong 0002},
  year = {2024},
  month = {January},
  doi = {10.1109/TPDS.2023.3332711},
  url = {https://doi.org/10.1109/TPDS.2023.3332711},
  researchr = {https://researchr.org/publication/JiangYFGAD24},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. Parallel Distrib. Syst.},
  volume = {35},
  number = {1},
  pages = {89-104},
}