Weiwen Jiang, Qingfeng Zhuge, Xianzhang Chen, Lei Yang, Juan Yi, Edwin Hsing-Mean Sha. Properties of Self-Timed Ring Architectures for Deadlock-Free and Consistent Configuration Reaching Maximum Throughput. VLSI Signal Processing, 84(1):123-137, 2016. [doi]
@article{JiangZCYYS16,
title = {Properties of Self-Timed Ring Architectures for Deadlock-Free and Consistent Configuration Reaching Maximum Throughput},
author = {Weiwen Jiang and Qingfeng Zhuge and Xianzhang Chen and Lei Yang and Juan Yi and Edwin Hsing-Mean Sha},
year = {2016},
doi = {10.1007/s11265-015-0984-6},
url = {http://dx.doi.org/10.1007/s11265-015-0984-6},
researchr = {https://researchr.org/publication/JiangZCYYS16},
cites = {0},
citedby = {0},
journal = {VLSI Signal Processing},
volume = {84},
number = {1},
pages = {123-137},
}