Hao Jiang, Jiapei Zheng, Yunzhengmao Wang, Jinshan Zhang, Haozhe Zhu, Liangjian Lyu, Yingping Chen, Chixiao Chen, Qi Liu. A $2.53 \mu \mathrm{W}/\text{channel}$ Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros. In IEEE International Symposium on Circuits and Systems, ISCAS 2023, Monterey, CA, USA, May 21-25, 2023. pages 1-5, IEEE, 2023. [doi]
@inproceedings{JiangZWZZLCCL23,
title = {A $2.53 \mu \mathrm{W}/\text{channel}$ Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros},
author = {Hao Jiang and Jiapei Zheng and Yunzhengmao Wang and Jinshan Zhang and Haozhe Zhu and Liangjian Lyu and Yingping Chen and Chixiao Chen and Qi Liu},
year = {2023},
doi = {10.1109/ISCAS46773.2023.10181615},
url = {https://doi.org/10.1109/ISCAS46773.2023.10181615},
researchr = {https://researchr.org/publication/JiangZWZZLCCL23},
cites = {0},
citedby = {0},
pages = {1-5},
booktitle = {IEEE International Symposium on Circuits and Systems, ISCAS 2023, Monterey, CA, USA, May 21-25, 2023},
publisher = {IEEE},
isbn = {978-1-6654-5109-3},
}