On Gate Level Power Optimization of Combinational Circuits Using Pseudo Power Gating

Yu Jin, Shinji Kimura. On Gate Level Power Optimization of Combinational Circuits Using Pseudo Power Gating. IEICE Transactions, 95-A(12):2191-2198, 2012. [doi]

Authors

Yu Jin

This author has not been identified. Look up 'Yu Jin' in Google

Shinji Kimura

This author has not been identified. Look up 'Shinji Kimura' in Google