Top-down modeling of RISC processors in VHDL - researchr publication authors

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Hsiao-Ping Juan, Nancy D. Holmes, Smita Bakshi, Daniel D. Gajski. Top-down modeling of RISC processors in VHDL. In Proceedings of the European Design Automation Conference 1993, EURO-DAC '93 with EURO-VHDL'93, Hamburg, Germany, September 20-24, 1993. pages 454-459, IEEE Computer Society, 1993. [doi]

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