Design of a Fault Tolerant Multistage Interconnection Network with Parallel Duplicated Switches - researchr publication authors

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Naotake Kamiura, Takashi Kodera, Nobuyuki Matsui. Design of a Fault Tolerant Multistage Interconnection Network with Parallel Duplicated Switches. In 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings. pages 143, IEEE Computer Society, 2000. [doi]

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