Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto. Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design. IEICE Transactions, 89-A(12):3560-3568, 2006. [doi]
@article{KanamotoITOH06,
title = {Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design},
author = {Toshiki Kanamoto and Tatsuhiko Ikeda and Akira Tsuchiya and Hidetoshi Onodera and Masanori Hashimoto},
year = {2006},
doi = {10.1093/ietfec/e89-a.12.3560},
url = {http://dx.doi.org/10.1093/ietfec/e89-a.12.3560},
tags = {modeling, context-aware, design},
researchr = {https://researchr.org/publication/KanamotoITOH06},
cites = {0},
citedby = {0},
journal = {IEICE Transactions},
volume = {89-A},
number = {12},
pages = {3560-3568},
}