Avadhoot Khairnar, Bhavuk Chauhan, Geetanjali Sharma, Amit M. Joshi 0001. High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logic. Journal of Circuits, Systems, and Computers, 31(11), 2022. [doi]
@article{KhairnarCSJ22,
title = {High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logic},
author = {Avadhoot Khairnar and Bhavuk Chauhan and Geetanjali Sharma and Amit M. Joshi 0001},
year = {2022},
doi = {10.1142/S0218126622502000},
url = {https://doi.org/10.1142/S0218126622502000},
researchr = {https://researchr.org/publication/KhairnarCSJ22},
cites = {0},
citedby = {0},
journal = {Journal of Circuits, Systems, and Computers},
volume = {31},
number = {11},
}