Design Optimization of On-Chip Inductive Peaking Structures for 0.13-μm CMOS 40-Gb/s Transmitter Circuits

Jaeha Kim, Jeong-Kyoum Kim, Bong-Joon Lee, Deog Kyoon Jeong. Design Optimization of On-Chip Inductive Peaking Structures for 0.13-μm CMOS 40-Gb/s Transmitter Circuits. IEEE Trans. on Circuits and Systems, 56-I(12):2544-2555, 2009. [doi]

@article{KimKLJ09,
  title = {Design Optimization of On-Chip Inductive Peaking Structures for 0.13-μm CMOS 40-Gb/s Transmitter Circuits},
  author = {Jaeha Kim and Jeong-Kyoum Kim and Bong-Joon Lee and Deog Kyoon Jeong},
  year = {2009},
  doi = {10.1109/TCSI.2009.2023772},
  url = {http://dx.doi.org/10.1109/TCSI.2009.2023772},
  researchr = {https://researchr.org/publication/KimKLJ09},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. on Circuits and Systems},
  volume = {56-I},
  number = {12},
  pages = {2544-2555},
}