Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS

Rajani Kuchipudi, Hamid Mahmoodi. Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS. In 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA. pages 27-32, IEEE Computer Society, 2007. [doi]

@inproceedings{KuchipudiM07,
  title = {Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS},
  author = {Rajani Kuchipudi and Hamid Mahmoodi},
  year = {2007},
  doi = {10.1109/ISQED.2007.151},
  url = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2007.151},
  tags = {optimization, logic},
  researchr = {https://researchr.org/publication/KuchipudiM07},
  cites = {0},
  citedby = {0},
  pages = {27-32},
  booktitle = {8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA},
  publisher = {IEEE Computer Society},
  isbn = {978-0-7695-2795-6},
}