Design of Practical Parity Generator and Parity Checker Circuits in QCA

Dharmendra Kumar, Chintoo Kumar, Shipra Gautam, Debasis Mitra 0002. Design of Practical Parity Generator and Parity Checker Circuits in QCA. In IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2017, Bhopal, India, December 18-20, 2017. pages 28-33, IEEE, 2017. [doi]

@inproceedings{KumarKG017,
  title = {Design of Practical Parity Generator and Parity Checker Circuits in QCA},
  author = {Dharmendra Kumar and Chintoo Kumar and Shipra Gautam and Debasis Mitra 0002},
  year = {2017},
  doi = {10.1109/iNIS.2017.16},
  url = {http://doi.ieeecomputersociety.org/10.1109/iNIS.2017.16},
  researchr = {https://researchr.org/publication/KumarKG017},
  cites = {0},
  citedby = {0},
  pages = {28-33},
  booktitle = {IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2017, Bhopal, India, December 18-20, 2017},
  publisher = {IEEE},
  isbn = {978-1-5386-1356-6},
}