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Experimental Estimation of Parasitic Capacitance of Thermal Interface Material Using Double Pulse Test Circuit under Realistic Operating Conditions

Kalyani V. Lande, J. Satheesh Reddy, Arun Karuppaswamy B. Experimental Estimation of Parasitic Capacitance of Thermal Interface Material Using Double Pulse Test Circuit under Realistic Operating Conditions. In 50th Annual Conference of the IEEE Industrial Electronics Society, IECON 2024, Chicago, IL, USA, November 3-6, 2024. pages 1-6, IEEE, 2024. [doi]

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