Jri Lee, Ping-Chuan Chiang, Chih-Chi Weng. 56Gb/s PAM4 and NRZ SerDes transceivers in 40nm CMOS. In Symposium on VLSI Circuits, VLSIC 2015, Kyoto, Japan, June 17-19, 2015. pages 118, IEEE, 2015. [doi]
@inproceedings{LeeCW15-0,
title = {56Gb/s PAM4 and NRZ SerDes transceivers in 40nm CMOS},
author = {Jri Lee and Ping-Chuan Chiang and Chih-Chi Weng},
year = {2015},
doi = {10.1109/VLSIC.2015.7231346},
url = {http://dx.doi.org/10.1109/VLSIC.2015.7231346},
researchr = {https://researchr.org/publication/LeeCW15-0},
cites = {0},
citedby = {0},
pages = {118},
booktitle = {Symposium on VLSI Circuits, VLSIC 2015, Kyoto, Japan, June 17-19, 2015},
publisher = {IEEE},
isbn = {978-4-86348-502-0},
}