Sang Min Lee, Dongwon Seo, Shahin Mehdizad Taleie, Derui Kong, Michael Joseph McGowan, Tongyu Song, Ganesh R. Saripalli, Jenny Kuo, Seyfi S. Bazarjani. A 14b 750MS/s DAC in 20nm CMOS with <-168dBm/Hz noise floor beyond Nyquist and 79dBc SFDR utilizing a low glitch-noise hybrid R-2R architecture. In Symposium on VLSI Circuits, VLSIC 2015, Kyoto, Japan, June 17-19, 2015. pages 164, IEEE, 2015. [doi]
@inproceedings{LeeSTKMSSKB15,
title = {A 14b 750MS/s DAC in 20nm CMOS with <-168dBm/Hz noise floor beyond Nyquist and 79dBc SFDR utilizing a low glitch-noise hybrid R-2R architecture},
author = {Sang Min Lee and Dongwon Seo and Shahin Mehdizad Taleie and Derui Kong and Michael Joseph McGowan and Tongyu Song and Ganesh R. Saripalli and Jenny Kuo and Seyfi S. Bazarjani},
year = {2015},
doi = {10.1109/VLSIC.2015.7231251},
url = {http://dx.doi.org/10.1109/VLSIC.2015.7231251},
researchr = {https://researchr.org/publication/LeeSTKMSSKB15},
cites = {0},
citedby = {0},
pages = {164},
booktitle = {Symposium on VLSI Circuits, VLSIC 2015, Kyoto, Japan, June 17-19, 2015},
publisher = {IEEE},
isbn = {978-4-86348-502-0},
}