Fully Row/Column-Parallel In-memory Computing SRAM Macro employing Capacitor-based Mixed-signal Computation with 5-b Inputs

Jinseok Lee, Hossein Valavi, Yinqi Tang, Naveen Verma. Fully Row/Column-Parallel In-memory Computing SRAM Macro employing Capacitor-based Mixed-signal Computation with 5-b Inputs. In 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021. pages 1-2, IEEE, 2021. [doi]

@inproceedings{LeeVTV21,
  title = {Fully Row/Column-Parallel In-memory Computing SRAM Macro employing Capacitor-based Mixed-signal Computation with 5-b Inputs},
  author = {Jinseok Lee and Hossein Valavi and Yinqi Tang and Naveen Verma},
  year = {2021},
  doi = {10.23919/VLSICircuits52068.2021.9492444},
  url = {https://doi.org/10.23919/VLSICircuits52068.2021.9492444},
  researchr = {https://researchr.org/publication/LeeVTV21},
  cites = {0},
  citedby = {0},
  pages = {1-2},
  booktitle = {2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021},
  publisher = {IEEE},
  isbn = {978-4-86348-780-2},
}