A compact AES core with on-line error-detection for FPGA applications with modest hardware resources

Uros Legat, Anton Biasizzo, Franc Novak. A compact AES core with on-line error-detection for FPGA applications with modest hardware resources. Microprocessors and Microsystems, 35(4):405-416, 2011. [doi]

@article{LegatBN11-0,
  title = {A compact AES core with on-line error-detection for FPGA applications with modest hardware resources},
  author = {Uros Legat and Anton Biasizzo and Franc Novak},
  year = {2011},
  doi = {10.1016/j.micpro.2011.03.001},
  url = {http://dx.doi.org/10.1016/j.micpro.2011.03.001},
  researchr = {https://researchr.org/publication/LegatBN11-0},
  cites = {0},
  citedby = {0},
  journal = {Microprocessors and Microsystems},
  volume = {35},
  number = {4},
  pages = {405-416},
}