The following publications are possibly variants of this publication:
- A worst case timing analysis technique for instruction prefetch buffersMinsuk Lee, Sang Lyul Min, Chong-Sang Kim. jsa, 40(10-12):681-684, 1994. [doi]
- An Accurate Worst Case Timing Analysis Technique for RISC ProcessorsSung-Soo Lim, Young Hyun Bae, Gyu Tae Jang, Byung-Do Rhee, Sang Lyul Min, Chang Yun Park, Heonshik Shin, Kunsoo Park, Chong-Sang Kim. rtss 1994: 142-151
- A Worst Case Timing Analysis Technique for Optimized ProgramsSung-Soo Lim, Jihong Kim, Sang Lyul Min. rtcsa 1998: 151-157 [doi]
- Worst Case Timing Analysis of RISC Processors: R3000/R3010 Case StudyYerang Hur, Young Hyun Bae, Sung-Soo Lim, Sung-Kwan Kim, Byung-Do Rhee, Sang Lyul Min, Chang Yun Park, Heonshik Shin, Chong-Sang Kim. rtss 1995: 308-321
- An Accurate Worst Case Timing Analysis for RISC ProcessorsSung-Soo Lim, Young Hyun Bae, Gyu Tae Jang, Byung-Do Rhee, Sang Lyul Min, Chang Yun Park, Heonshik Shin, Kunsoo Park, Soo-Mook Moon, Chong-Sang Kim. TSE, 21(7):593-604, 1995. [doi]
- Efficient worst case timing analysis of data cachingSung-Kwan Kim, Sang Lyul Min, Rhan Ha. rtas 1996: 230-240 [doi]