Hardware Design of Low-Power High-Throughput Sorting Unit

Shih-Hsiang Lin, Pei-Yin Chen, Yu-Ning Lin. Hardware Design of Low-Power High-Throughput Sorting Unit. IEEE Transactions on Computers, 66(8):1383-1395, 2017. [doi]

Authors

Shih-Hsiang Lin

This author has not been identified. Look up 'Shih-Hsiang Lin' in Google

Pei-Yin Chen

This author has not been identified. Look up 'Pei-Yin Chen' in Google

Yu-Ning Lin

This author has not been identified. Look up 'Yu-Ning Lin' in Google