Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Cheng-Che Ho. A high speed and energy efficient full adder design using complementary & level restoring carry logic. In International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece. IEEE, 2006. [doi]
@inproceedings{LinHSH06,
title = {A high speed and energy efficient full adder design using complementary & level restoring carry logic},
author = {Jin-Fa Lin and Yin-Tsung Hwang and Ming-Hwa Sheu and Cheng-Che Ho},
year = {2006},
doi = {10.1109/ISCAS.2006.1693182},
url = {http://dx.doi.org/10.1109/ISCAS.2006.1693182},
tags = {logic, design},
researchr = {https://researchr.org/publication/LinHSH06},
cites = {0},
citedby = {0},
booktitle = {International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece},
publisher = {IEEE},
}