Chih-Hsiang Lin, James B. Kuo. Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT Technique. In José C. Monteiro, Rene van Leuken, editors, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers. Volume 5953 of Lecture Notes in Computer Science, pages 127-135, Springer, 2009. [doi]
@inproceedings{LinK09-2,
title = {Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT Technique},
author = {Chih-Hsiang Lin and James B. Kuo},
year = {2009},
doi = {10.1007/978-3-642-11802-9_17},
url = {http://dx.doi.org/10.1007/978-3-642-11802-9_17},
tags = {optimization, design},
researchr = {https://researchr.org/publication/LinK09-2},
cites = {0},
citedby = {0},
pages = {127-135},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers},
editor = {José C. Monteiro and Rene van Leuken},
volume = {5953},
series = {Lecture Notes in Computer Science},
publisher = {Springer},
isbn = {978-3-642-11801-2},
}