A general cost-effective design structure for probabilistic-based noise-tolerant logic functions in nanometer CMOS technology

Kaikai Liu, Ting An, Hao Cai, Lirida A. B. Naviner, Jean-François Naviner, Hervé Petit. A general cost-effective design structure for probabilistic-based noise-tolerant logic functions in nanometer CMOS technology. In Proceedings of Eurocon 2013, International Conference on Computer as a Tool, Zagreb, Croatia, July 1-4, 2013. pages 1829-1836, IEEE, 2013. [doi]

@inproceedings{LiuACNNP13,
  title = {A general cost-effective design structure for probabilistic-based noise-tolerant logic functions in nanometer CMOS technology},
  author = {Kaikai Liu and Ting An and Hao Cai and Lirida A. B. Naviner and Jean-François Naviner and Hervé Petit},
  year = {2013},
  doi = {10.1109/EUROCON.2013.6625225},
  url = {http://dx.doi.org/10.1109/EUROCON.2013.6625225},
  researchr = {https://researchr.org/publication/LiuACNNP13},
  cites = {0},
  citedby = {0},
  pages = {1829-1836},
  booktitle = {Proceedings of Eurocon 2013, International Conference on Computer as a Tool, Zagreb, Croatia, July 1-4, 2013},
  publisher = {IEEE},
  isbn = {978-1-4673-2230-0},
}