FPGA Implementation of A Hybrid Decoder for STT-MRAM

Xue Liu, Kui Cai, Zhen Mei. FPGA Implementation of A Hybrid Decoder for STT-MRAM. In 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018, Chengdu, China, October 26-30, 2018. pages 325-328, IEEE, 2018. [doi]

@inproceedings{LiuCM18-3,
  title = {FPGA Implementation of A Hybrid Decoder for STT-MRAM},
  author = {Xue Liu and Kui Cai and Zhen Mei},
  year = {2018},
  doi = {10.1109/APCCAS.2018.8605688},
  url = {https://doi.org/10.1109/APCCAS.2018.8605688},
  researchr = {https://researchr.org/publication/LiuCM18-3},
  cites = {0},
  citedby = {0},
  pages = {325-328},
  booktitle = {2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018, Chengdu, China, October 26-30, 2018},
  publisher = {IEEE},
  isbn = {978-1-5386-8240-1},
}