4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic

Yongpan Liu, Zhibo Wang, Albert Lee, Fang Su, Chieh-Pu Lo, Zhe Yuan, Chien-Chen Lin, Qi Wei, Yu Wang, Ya-Chin King, Chrong Jung Lin, Pedram Khalili, Kang-Lung Wang, Meng-Fan Chang, Huazhong Yang. 4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic. In 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016. pages 84-86, IEEE, 2016. [doi]

@inproceedings{LiuWLSLYLWWKLKW16,
  title = {4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic},
  author = {Yongpan Liu and Zhibo Wang and Albert Lee and Fang Su and Chieh-Pu Lo and Zhe Yuan and Chien-Chen Lin and Qi Wei and Yu Wang and Ya-Chin King and Chrong Jung Lin and Pedram Khalili and Kang-Lung Wang and Meng-Fan Chang and Huazhong Yang},
  year = {2016},
  doi = {10.1109/ISSCC.2016.7417918},
  url = {http://dx.doi.org/10.1109/ISSCC.2016.7417918},
  researchr = {https://researchr.org/publication/LiuWLSLYLWWKLKW16},
  cites = {0},
  citedby = {0},
  pages = {84-86},
  booktitle = {2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016},
  publisher = {IEEE},
  isbn = {978-1-4673-9467-3},
}