Chin-Yang Lo, Po-Tsang Huang, Wei Hwang. Energy-Efficient Accelerator Design with 3D-SRAM and Hierarchical Interconnection Architecture for Compact Sparse CNNs. In 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2020, Genova, Italy, August 31 - September 2, 2020. pages 320-323, IEEE, 2020. [doi]
@inproceedings{LoHH20,
title = {Energy-Efficient Accelerator Design with 3D-SRAM and Hierarchical Interconnection Architecture for Compact Sparse CNNs},
author = {Chin-Yang Lo and Po-Tsang Huang and Wei Hwang},
year = {2020},
doi = {10.1109/AICAS48895.2020.9073944},
url = {https://doi.org/10.1109/AICAS48895.2020.9073944},
researchr = {https://researchr.org/publication/LoHH20},
cites = {0},
citedby = {0},
pages = {320-323},
booktitle = {2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2020, Genova, Italy, August 31 - September 2, 2020},
publisher = {IEEE},
isbn = {978-1-7281-4922-6},
}