Hang Lu, Liang Chang, Chenglong Li, Zixuan Zhu, Shengjian Lu, Yanhuan Liu, Mingzhe Zhang. Distilling Bit-level Sparsity Parallelism for General Purpose Deep Learning Acceleration. In MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, Virtual Event, Greece, October 18-22, 2021. pages 963-976, ACM, 2021. [doi]
@inproceedings{LuCLZLLZ21,
title = {Distilling Bit-level Sparsity Parallelism for General Purpose Deep Learning Acceleration},
author = {Hang Lu and Liang Chang and Chenglong Li and Zixuan Zhu and Shengjian Lu and Yanhuan Liu and Mingzhe Zhang},
year = {2021},
doi = {10.1145/3466752.3480123},
url = {https://doi.org/10.1145/3466752.3480123},
researchr = {https://researchr.org/publication/LuCLZLLZ21},
cites = {0},
citedby = {0},
pages = {963-976},
booktitle = {MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, Virtual Event, Greece, October 18-22, 2021},
publisher = {ACM},
isbn = {978-1-4503-8557-2},
}