Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process - researchr publication references

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Guangyi Lu, Yuan Wang, Xing Zhang. Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process. IEICE Transactions, 99-C(5):590-596, 2016. [doi]

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