Raúl MartÃnez, José M. Claver, Francisco José Alfaro, José L. Sánchez. Hardware Implementation Study of the Deficit Table Egress Link Scheduling Algorithm. In ICPP 2009, International Conference on Parallel Processing, Vienna, Austria, 22-25 September 2009. pages 26-33, IEEE Computer Society, 2009. [doi]
@inproceedings{MartinezCAS09,
title = {Hardware Implementation Study of the Deficit Table Egress Link Scheduling Algorithm},
author = {Raúl MartÃnez and José M. Claver and Francisco José Alfaro and José L. Sánchez},
year = {2009},
doi = {10.1109/ICPP.2009.65},
url = {http://doi.ieeecomputersociety.org/10.1109/ICPP.2009.65},
researchr = {https://researchr.org/publication/MartinezCAS09},
cites = {0},
citedby = {0},
pages = {26-33},
booktitle = {ICPP 2009, International Conference on Parallel Processing, Vienna, Austria, 22-25 September 2009},
publisher = {IEEE Computer Society},
isbn = {978-0-7695-3802-0},
}