A power-efficient hierarchical network-on-chip topology for stacked 3D ICs - researchr publication authors

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Debora Matos, Cezar Reinbrecht, Tiago Motta, Altamiro Amadeu Susin. A power-efficient hierarchical network-on-chip topology for stacked 3D ICs. In Martin Margala, Ricardo Augusto da Luz Reis, Alex Orailoglu, Luigi Carro, Luis Miguel Silveira, H. Fatih Ugurdag, editors, 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013. pages 308-313, IEEE, 2013. [doi]

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