Modeling the effect of NMOS gate capacitance in an on-chip decoupling capacitor PAA countermeasure

Matthew Mayhew, Radu Muresan. Modeling the effect of NMOS gate capacitance in an on-chip decoupling capacitor PAA countermeasure. In IEEE 57th International Midwest Symposium on Circuits and Systems, MWSCAS 2014, College Station, TX, USA, August 3-6, 2014. pages 121-124, IEEE, 2014. [doi]

@inproceedings{MayhewM14-0,
  title = {Modeling the effect of NMOS gate capacitance in an on-chip decoupling capacitor PAA countermeasure},
  author = {Matthew Mayhew and Radu Muresan},
  year = {2014},
  doi = {10.1109/MWSCAS.2014.6908367},
  url = {https://doi.org/10.1109/MWSCAS.2014.6908367},
  researchr = {https://researchr.org/publication/MayhewM14-0},
  cites = {0},
  citedby = {0},
  pages = {121-124},
  booktitle = {IEEE 57th International Midwest Symposium on Circuits and Systems, MWSCAS 2014, College Station, TX, USA, August 3-6, 2014},
  publisher = {IEEE},
  isbn = {978-1-4799-4134-6},
}