1.2V 300MHz CMOS PLL for clock generation in 0.35UM process - researchr publication references

researchr

You are not signed in
Sign in
Sign up

Deana McDonagh, K. I. Arshak, O. Abubaker. 1.2V 300MHz CMOS PLL for clock generation in 0.35UM process. In C. E. Palau Salvador, editor, Proceedings of the Fifth IASTED International Conference on Communication Systems and Networks, August 28-30, 2006, Palma de Mallorca, Spain. pages 243-247, IASTED/ACTA Press, 2006.

No references recorded for this publication.

No citations of this publication recorded.

runs on WebDSL