A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology

Yavar Safaei Mehrabani, Mohammad Eshghi. A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology. CSSP, 34(3):739-759, 2015. [doi]

@article{MehrabaniE15,
  title = {A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology},
  author = {Yavar Safaei Mehrabani and Mohammad Eshghi},
  year = {2015},
  doi = {10.1007/s00034-014-9887-1},
  url = {http://dx.doi.org/10.1007/s00034-014-9887-1},
  researchr = {https://researchr.org/publication/MehrabaniE15},
  cites = {0},
  citedby = {0},
  journal = {CSSP},
  volume = {34},
  number = {3},
  pages = {739-759},
}