Ugljesa Milic, Alejandro Rico, Paul M. Carpenter, Alex Ramírez. Sharing the instruction cache among lean cores on an asymmetric CMP for HPC applications. In 2017 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2017, Santa Rosa, CA, USA, April 24-25, 2017. pages 3-12, IEEE, 2017. [doi]
@inproceedings{MilicRCR17,
title = {Sharing the instruction cache among lean cores on an asymmetric CMP for HPC applications},
author = {Ugljesa Milic and Alejandro Rico and Paul M. Carpenter and Alex Ramírez},
year = {2017},
doi = {10.1109/ISPASS.2017.7975265},
url = {https://doi.org/10.1109/ISPASS.2017.7975265},
researchr = {https://researchr.org/publication/MilicRCR17},
cites = {0},
citedby = {0},
pages = {3-12},
booktitle = {2017 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2017, Santa Rosa, CA, USA, April 24-25, 2017},
publisher = {IEEE},
isbn = {978-1-5386-3890-3},
}