Influence of passive hardware redundancy on differential power analysis resistance of AES cipher implemented in FPGA

Vojtech Miskovský, Hana Kubátová, Martin Novotný. Influence of passive hardware redundancy on differential power analysis resistance of AES cipher implemented in FPGA. Microprocessors and Microsystems, 51:220-226, 2017. [doi]

@article{MiskovskyKN17,
  title = {Influence of passive hardware redundancy on differential power analysis resistance of AES cipher implemented in FPGA},
  author = {Vojtech Miskovský and Hana Kubátová and Martin Novotný},
  year = {2017},
  doi = {10.1016/j.micpro.2017.04.014},
  url = {https://doi.org/10.1016/j.micpro.2017.04.014},
  researchr = {https://researchr.org/publication/MiskovskyKN17},
  cites = {0},
  citedby = {0},
  journal = {Microprocessors and Microsystems},
  volume = {51},
  pages = {220-226},
}