Topology synthesis of analog circuits with yield optimization and evaluation using pareto fronts - researchr publication authors

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Oliver Mitea, Markus Meissner, Lars Hedrich. Topology synthesis of analog circuits with yield optimization and evaluation using pareto fronts. In IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011. pages 78-81, IEEE, 2011. [doi]

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