Design a Gated PMOS Spillage Reduction Approach for CMOS SRAM Cell in 90nm Technology Node

Deepak Mittal. Design a Gated PMOS Spillage Reduction Approach for CMOS SRAM Cell in 90nm Technology Node. In 14th International Conference on Computing Communication and Networking Technologies, ICCCNT 2023, Delhi, India, July 6-8, 2023. pages 1-4, IEEE, 2023. [doi]

@inproceedings{Mittal23-1,
  title = {Design a Gated PMOS Spillage Reduction Approach for CMOS SRAM Cell in 90nm Technology Node},
  author = {Deepak Mittal},
  year = {2023},
  doi = {10.1109/ICCCNT56998.2023.10307843},
  url = {https://doi.org/10.1109/ICCCNT56998.2023.10307843},
  researchr = {https://researchr.org/publication/Mittal23-1},
  cites = {0},
  citedby = {0},
  pages = {1-4},
  booktitle = {14th International Conference on Computing Communication and Networking Technologies, ICCCNT 2023, Delhi, India, July 6-8, 2023},
  publisher = {IEEE},
  isbn = {979-8-3503-3509-5},
}