A Disturb Free Read Port 8T SRAM Bitcell Circuit Design with Virtual Ground Scheme

Mahmood Uddin Mohammed, Nahid M. Hossain, Masud H. Chowdhury. A Disturb Free Read Port 8T SRAM Bitcell Circuit Design with Virtual Ground Scheme. In IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018, Windsor, ON, Canada, August 5-8, 2018. pages 412-415, IEEE, 2018. [doi]

@inproceedings{MohammedHC18,
  title = {A Disturb Free Read Port 8T SRAM Bitcell Circuit Design with Virtual Ground Scheme},
  author = {Mahmood Uddin Mohammed and Nahid M. Hossain and Masud H. Chowdhury},
  year = {2018},
  doi = {10.1109/MWSCAS.2018.8624107},
  url = {https://doi.org/10.1109/MWSCAS.2018.8624107},
  researchr = {https://researchr.org/publication/MohammedHC18},
  cites = {0},
  citedby = {0},
  pages = {412-415},
  booktitle = {IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018, Windsor, ON, Canada, August 5-8, 2018},
  publisher = {IEEE},
  isbn = {978-1-5386-7392-8},
}