Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits - researchr publication authors

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Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos. Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits. In Georges G. E. Gielen, editor, Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006. pages 1191-1196, European Design and Automation Association, Leuven, Belgium, 2006. [doi]

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