Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura. Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption. In Lars Svensson, José Monteiro, editors, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers. Volume 5349 of Lecture Notes in Computer Science, pages 62-71, Springer, 2008. [doi]
@inproceedings{MuroyamaIY08,
title = {Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption},
author = {Masanori Muroyama and Tohru Ishihara and Hiroto Yasuura},
year = {2008},
doi = {10.1007/978-3-540-95948-9_7},
url = {http://dx.doi.org/10.1007/978-3-540-95948-9_7},
tags = {power consumption, analysis},
researchr = {https://researchr.org/publication/MuroyamaIY08},
cites = {0},
citedby = {0},
pages = {62-71},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers},
editor = {Lars Svensson and José Monteiro},
volume = {5349},
series = {Lecture Notes in Computer Science},
publisher = {Springer},
isbn = {978-3-540-95947-2},
}