Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs

Sreenivaas S. Muthyala, Nur A. Touba. Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs. In Luc Claesen, MarĂ­a Teresa Sanz-Pascual, Ricardo Reis, Arturo Sarmiento-Reyes, editors, VLSI-SoC: Internet of Things Foundations - 22nd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2014, Playa del Carmen, Mexico, October 6-8, 2014, Revised and Extended Selected Papers. Volume 464 of IFIP Advances in Information and Communication Technology, pages 21-38, Springer, 2014. [doi]

Authors

Sreenivaas S. Muthyala

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Nur A. Touba

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