A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices

Alessandro Antonio Nacci, Vincenzo Rana, Francesco Bruschi, Donatella Sciuto, Ivan Beretta, David Atienza. A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices. In The 50th Annual Design Automation Conference 2013, DAC '13, Austin, TX, USA, May 29 - June 07, 2013. pages 52, ACM, 2013. [doi]

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