Design of Defect Tolerant Wallace Multiplier

Kazuteru Namba, Hideo Ito. Design of Defect Tolerant Wallace Multiplier. In 11th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2005), 12-14 December, 2005, Changsha, Hunan, China. pages 300-304, IEEE Computer Society, 2005. [doi]

@inproceedings{NambaI05:0,
  title = {Design of Defect Tolerant Wallace Multiplier},
  author = {Kazuteru Namba and Hideo Ito},
  year = {2005},
  doi = {10.1109/PRDC.2005.30},
  url = {http://doi.ieeecomputersociety.org/10.1109/PRDC.2005.30},
  tags = {design},
  researchr = {https://researchr.org/publication/NambaI05%3A0},
  cites = {0},
  citedby = {0},
  pages = {300-304},
  booktitle = {11th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2005), 12-14 December, 2005, Changsha, Hunan, China},
  publisher = {IEEE Computer Society},
  isbn = {0-7695-2492-3},
}