High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Naoya Onizawa, Akira Mochizuki, Hirokatsu Shirahama, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu. High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs. IEICE Transactions, 97-D(6):1546-1556, 2014. [doi]

This author has not been identified. Look up 'Naoya Onizawa' in GoogleThis author has not been identified. Look up 'Akira Mochizuki' in GoogleThis author has not been identified. Look up 'Hirokatsu Shirahama' in GoogleThis author has not been identified. Look up 'Masashi Imai' in GoogleThis author has not been identified. Look up 'Tomohiro Yoneda' in GoogleThis author has not been identified. Look up 'Takahiro Hanyu' in Google

runs on WebDSL