Low-Latency Digit-Serial Systolic Double Basis Multiplier over $\mbi GF{(2^m})$ Using Subquadratic Toeplitz Matrix-Vector Product Approach

Jeng-Shyang Pan, Reza Azarderakhsh, Mehran Mozaffari Kermani, Chiou-Yng Lee, Wen-Yo Lee, Che Wun Chiou, Jim-Min Lin. Low-Latency Digit-Serial Systolic Double Basis Multiplier over $\mbi GF{(2^m})$ Using Subquadratic Toeplitz Matrix-Vector Product Approach. IEEE Transactions on Computers, 63(5):1169-1181, 2014. [doi]

@article{PanAKLLCL14,
  title = {Low-Latency Digit-Serial Systolic Double Basis Multiplier over $\mbi GF{(2^m})$ Using Subquadratic Toeplitz Matrix-Vector Product Approach},
  author = {Jeng-Shyang Pan and Reza Azarderakhsh and Mehran Mozaffari Kermani and Chiou-Yng Lee and Wen-Yo Lee and Che Wun Chiou and Jim-Min Lin},
  year = {2014},
  doi = {10.1109/TC.2012.239},
  url = {http://doi.ieeecomputersociety.org/10.1109/TC.2012.239},
  researchr = {https://researchr.org/publication/PanAKLLCL14},
  cites = {0},
  citedby = {0},
  journal = {IEEE Transactions on Computers},
  volume = {63},
  number = {5},
  pages = {1169-1181},
}