Ivan Miro Panades, Alain Greiner. Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures. In First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings. pages 83-94, IEEE Computer Society, 2007. [doi]
@inproceedings{PanadesG07,
title = {Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures},
author = {Ivan Miro Panades and Alain Greiner},
year = {2007},
doi = {10.1109/NOCS.2007.14},
url = {http://doi.ieeecomputersociety.org/10.1109/NOCS.2007.14},
tags = {architecture},
researchr = {https://researchr.org/publication/PanadesG07},
cites = {0},
citedby = {0},
pages = {83-94},
booktitle = {First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings},
publisher = {IEEE Computer Society},
isbn = {978-0-7695-2773-4},
}