Novel Low Power FinFET SRAM Cell Design With Better Read and Writabilty For Cache Memory

Shreyash Patel, Youngbae Kim, Ken Choi. Novel Low Power FinFET SRAM Cell Design With Better Read and Writabilty For Cache Memory. In International SoC Design Conference, ISOCC 2018, Daegu, South Korea, November 12-15, 2018. pages 44-45, IEEE, 2018. [doi]

@inproceedings{PatelKC18,
  title = {Novel Low Power FinFET SRAM Cell Design With Better Read and Writabilty For Cache Memory},
  author = {Shreyash Patel and Youngbae Kim and Ken Choi},
  year = {2018},
  doi = {10.1109/ISOCC.2018.8649900},
  url = {https://doi.org/10.1109/ISOCC.2018.8649900},
  researchr = {https://researchr.org/publication/PatelKC18},
  cites = {0},
  citedby = {0},
  pages = {44-45},
  booktitle = {International SoC Design Conference, ISOCC 2018, Daegu, South Korea, November 12-15, 2018},
  publisher = {IEEE},
  isbn = {978-1-5386-7960-9},
}