An address generator approach to the hardware implementation of a scalable Pease FFT core - researchr publication authors

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Agenor Polo, Manuel Jimenez, David Marquez, Domingo Rodríguez. An address generator approach to the hardware implementation of a scalable Pease FFT core. In 55th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2012, Boise, ID, USA, August 5-8, 2012. pages 832-835, IEEE, 2012. [doi]

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