An instruction scratchpad memory allocation for the precision timed architecture

Aayush Prakash, Hiren D. Patel. An instruction scratchpad memory allocation for the precision timed architecture. In Wolfgang Rosenstiel, Lothar Thiele, editors, 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012. pages 659-664, IEEE, 2012. [doi]

@inproceedings{PrakashP12,
  title = {An instruction scratchpad memory allocation for the precision timed architecture},
  author = {Aayush Prakash and Hiren D. Patel},
  year = {2012},
  url = {http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=6176553},
  researchr = {https://researchr.org/publication/PrakashP12},
  cites = {0},
  citedby = {0},
  pages = {659-664},
  booktitle = {2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012},
  editor = {Wolfgang Rosenstiel and Lothar Thiele},
  publisher = {IEEE},
  isbn = {978-1-4577-2145-8},
}