Daniel Prashanth, Hae-Seung Lee. A Sampling Clock Skew Correction Technique for Time-Interleaved SAR ADCs. In Ayse Kivilcim Coskun, Martin Margala, Laleh Behjat, Jie Han, editors, Proceedings of the 26th edition on Great Lakes Symposium on VLSI, GLVLSI 2016, Boston, MA, USA, May 18-20, 2016. pages 129-132, ACM, 2016. [doi]
@inproceedings{PrashanthL16,
title = {A Sampling Clock Skew Correction Technique for Time-Interleaved SAR ADCs},
author = {Daniel Prashanth and Hae-Seung Lee},
year = {2016},
doi = {10.1145/2902961.2903008},
url = {http://doi.acm.org/10.1145/2902961.2903008},
researchr = {https://researchr.org/publication/PrashanthL16},
cites = {0},
citedby = {0},
pages = {129-132},
booktitle = {Proceedings of the 26th edition on Great Lakes Symposium on VLSI, GLVLSI 2016, Boston, MA, USA, May 18-20, 2016},
editor = {Ayse Kivilcim Coskun and Martin Margala and Laleh Behjat and Jie Han},
publisher = {ACM},
isbn = {978-1-4503-4274-2},
}