Preethi, K. G. Mohan, K. Sudeendra Kumar, K. K. Mahapatra. Low Power Sorters Using Clock Gating. In IEEE International Symposium on Smart Electronic Systems, iSES 2021, Jaipur, India, December 18-22, 2021. pages 6-11, IEEE, 2021. [doi]
@inproceedings{PreethiMKM21,
title = {Low Power Sorters Using Clock Gating},
author = {Preethi and K. G. Mohan and K. Sudeendra Kumar and K. K. Mahapatra},
year = {2021},
doi = {10.1109/iSES52644.2021.00015},
url = {https://doi.org/10.1109/iSES52644.2021.00015},
researchr = {https://researchr.org/publication/PreethiMKM21},
cites = {0},
citedby = {0},
pages = {6-11},
booktitle = {IEEE International Symposium on Smart Electronic Systems, iSES 2021, Jaipur, India, December 18-22, 2021},
publisher = {IEEE},
isbn = {978-1-7281-8753-2},
}